// test netlist for spectre
// Generated for: spectre
// Generated on: May 14 00:15:55 2002
// Design library name: PLL.behavioral
// Design cell name: example_phase_domain
// Design view name: schematic
simulator lang=spectre
global 0
include "/software/cadence01/tools.hppa/dfII/samples/artist/ahdlLib/quantity.spectre"

// Library name: PLL.behavioral
// Cell name: example_phase_domain
// View name: schematic
I32 (net35 net20 net50) generic_divider
I22 (net20 control_voltage) vco_tuning_curve f0=1.4175 v0=2.5 f1=5.167 \
        f2=0 f3=0 f4=0 vmax=10 vmin=-10
I30 (net11 control_voltage duty_cycle control_voltage) lock_indicator \
        top_chg_pmp_rail=10 bot_chg_pmp_rail=-10 max_vco_control=10 \
        min_vco_control=-10
I23 (control_voltage duty_cycle) charge_pump vmax=10 vmin=-10
I19 (duty_cycle net18 net19) rel_phase_pfd
V1 (net18 0) vsource dc=750.0m mag=0 type=dc
V6 (net35 net26) vsource dc=0 type=pulse val0=0 val1=2 period=40 delay=15m \
        rise=120n fall=130n width=120m
R9 (net11 0) resistor r=1k
R15 (control_voltage net62) resistor r=500
C10 (control_voltage 0) capacitor c=17n
C9 (net62 0) capacitor c=1.9u
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    sensfile="../psf/sens.output" 
tran tran stop=200m write="spectre.ic" writefinal="spectre.fc" \
    annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
saveOptions options save=allpub
ahdl_include "/software/cadence01/tools.hppa/dfII/samples/artist/pllLib/divider_phase_domain/veriloga/veriloga.va"